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this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 1 en25qh256 rev. e, issue date: 2012 / 01/30 features ? single power supply operation - full voltage range: 2.7-3.6 volt ? serial interface architecture - spi compatible: mode 0 and mode 3 ? 256 m-bit serial flash - 256 m-bit/32,768 k-byte/131,072 pages - 256 bytes per programmable page ? standard, dual or quad spi - standard spi: clk, cs#, di, do, wp#, hold# - dual spi: clk, cs#, dq 0 , dq 1 , wp#, hold# - quad spi: clk, cs#, dq 0 , dq 1 , dq 2 , dq 3 ? high performance - 80mhz clock rate for standard spi - 80mhz clock rate for two data bits - 50mhz clock rate for four data bits ? low power consumption - 12 ma typical active current - 1 a typical power down current ? uniform sector architecture: - 8192 sectors of 4-kbyte - 512 blocks of 64-kbyte - any sector or block can be erased individually ? software and hardware write protection: - write protect all or portion of memory via software - enable/disable protection with wp# pin ? high performance program/erase speed - page program time: 0.8ms typical - sector erase time: 50ms typical - block erase time 400ms typical - chip erase time: 100 seconds typical ? lockable 512 byte otp security sector ? support serial flash discoverable parameters (sfdp) signature ? read unique id number ? support high bank latch mode ? minimum 100k endurance cycle ? package options - 8 contact vdfn (6x8mm) - 16 pins sop 300mil body width - 24 balls bga (6x8mm) - all pb-free packages are rohs compliant ? industrial temperature range general description the en25qh256 is a 256 megabit (32,768 k-byte) serial flash memory, with enhanced write protection mechanisms. the en25qh256 supports the standard serial peripheral interface (spi), and a high performance dual/quad output as well as dual/quad i/o using spi pins: serial clock, chip select, serial dq 0 (di), dq 1 (do), dq 2 (wp#) and dq 3 (hold#). spi clock frequencies of up to 80mhz are supported allowing equivalent clock rates of 160mhz (80mhz x 2) for dual output when using the dual output fast read instructions, and spi clock frequencies of up to 50mhz are supported allowing equivalent clock rates of 200mhz (50mhz x 4) for quad output when using the quad output fast read instructions. the memory can be programmed 1 to 256 bytes at a time, using the page program instruction. the en25qh256 is designed to allow either single sector/block at a time or full chip erase operation. the en25qh256 can be configured to protect part of the memory as the software protected mode. the device can sustain a minimum of 100k program/erase cycles on each sector or block . en25qh256 256 me g abit serial flash memor y with 4kb y te uniform sector
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 2 en25qh256 rev. e, issue date: 2012 / 01/30 figure.1 connection diagrams 16 - lead sop 8 - lead vdfn do (dq 1 ) wp# (dq 2 ) vss cs# di (dq 0 ) clk hold# (dq 3 ) vcc 1 2 3 4 8 7 6 5
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 3 en25qh256 rev. e, issue date: 2012 / 01/30 top view, balls facing down 24 - ball bga
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 4 en25qh256 rev. e, issue date: 2012 / 01/30 figure 2. block diagram note: 1. dq 0 and dq 1 are used for dual and quad instructions. 2. dq 0 ~ dq 3 are used for quad instructions.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 5 en25qh256 rev. e, issue date: 2012 / 01/30 table 1. pin names symbol pin name clk serial clock input di (dq 0 ) serial data input (data input output 0) *1 do (dq 1 ) serial data output (data input output 1) *1 cs# chip select wp# (dq 2 ) write protect (data input output 2) *2 hold# (dq 3 ) hold# pin (data input output 3) *2 vcc supply voltage (2.7-3.6v) vss ground nc no connect note: 1. dq 0 and dq 1 are used for dual and quad instructions. 2. dq 2 ~ dq 3 are used for quad instructions. signal description serial data input, output and ios (di, do and dq 0 , dq 1 , dq 2 , dq 3 ) the en25qh256 support standard spi, dual spi and quad spi operation. standard spi instructions use the unidirectional di (input) pin to serially write instruct ions, addresses or data to the device on the rising edge of the serial clock (clk) input pin. standard spi also uses the unidirectional do (output) to read data or status from the device on the falling edge clk. dual and quad spi instruction use the bidirectional io pins to serially write instruction, addresses or data to the device on the rising ed ge of clk and read data or status from the device on the falling edge of clk. serial clock (clk) the spi serial clock input (clk) pin provides the timing for serial input and output operations. ("see spi mode") chip select (cs#) the spi chip select (cs#) pin enables and disables device operation. when cs# is high the device is deselected and the serial data output (do, or dq 0 , dq 1 , dq 2 and dq 3 ) pins are at high impedance. when deselected, the device s power consumption will be at standby levels unless an internal erase, program or status register cycle is in progress. wh en cs# is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. after power-up , cs# must transition from high to low before a new instruction will be accepted. hold (hold#) the hold# pin allows the device to be paused while it is actively selected. when hold# is brought low, while cs# is low, th e do pin will be at high impedance and signals on the di and clk pins will be ignored (don?t care). the hold function can be useful when multiple devices are sharing the same spi signals. the hold# function is only available for standard spi and dual spi operation, when during quad spi, this pin is the serial data io (dq 3 ) for quad i/o operation. write protect (wp#) the write protect (wp#) pin can be used to prevent the status register from being written. used in conjunction with the status register?s block protect (bp0, bp1, bp2 and bp3) bits and status register protect (srp) bits, a portion or the entire memory array can be hardware protected. the wp# function is only available for standard spi and dual spi operation, when during quad spi, this pin is the serial data io (dq 2 ) for quad i/o operation.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 6 en25qh256 rev. e, issue date: 2012 / 01/30 memory organization the memory is organized as: z 33,554,432 bytes z uniform sector architecture 512 blocks of 64-kbyte 8,192 sectors of 4-kbyte 131,072 pages (256 bytes each) each page can be individually programmed (bits are programmed from 1 to 0). the device is sector, block or chip erasable but not page erasable.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 7 en25qh256 rev. e, issue date: 2012 / 01/30 table 2. uniform block sector architecture ( 1/8 ) block sector address range block sector address range 8191 1fff000h 1ffffffh 7935 1eff000h 1efffffh ?. ?. ?. ?. ?. ?. 511 8176 1ff0000h 1ff0fffh 495 7920 1ef0000h 1ef0fffh 8175 1fef000h 1feffffh 7919 1eef000h 1eeffffh ?. ?. ?. ?. ?. ?. 510 8160 1fe0000h 1fe0fffh 494 7904 1ee0000h 1ee0fffh 8159 1fdf000h 1fdffffh 7903 1edf000h 1edffffh ?. ?. ?. ?. ?. ?. 509 8144 1fd0000h 1fd0fffh 493 7888 1ed0000h 1ed0fffh ?. ?. ?. ?. ?. ?. ?. ?. 7983 1f2f000h 1f2ffffh 7727 1e2f000h 1e2ffffh ?. ?. ?. ?. ?. ?. 498 7968 1f20000h 1f20fffh 482 7712 1e20000h 1e20fffh 7967 1f1f000h 1f1ffffh 7711 1e1f000h 1e1ffffh ?. ?. ?. ?. ?. ?. 497 7952 1f10000h 1f10fffh 481 7696 1e10000h 1e10fffh 7951 1f0f000h 1f0ffffh 7695 1e0f000h 1e0ffffh ?. ?. ?. ?. ?. ?. 496 7936 1f00000h 1f00fffh 480 7680 1e00000h 1e00fffh block sector address range block sector address range 7679 1dff000h 1dfffffh 7423 1cff000h 1cfffffh ?. ?. ?. ?. ?. ?. 479 7664 1df0000h 1df0fffh 463 7408 1cf0000h 1cf0fffh 7663 1def000h 1deffffh 7407 1cef000h 1ceffffh ?. ?. ?. ?. ?. ?. 478 7648 1de0000h 1de0fffh 462 7392 1ce0000h 1ce0fffh 7647 1ddf000h 1ddffffh 7391 1cdf000h 1cdffffh ?. ?. ?. ?. ?. ?. 477 7632 1dd0000h 1dd0fffh 461 7376 1cd0000h 1cd0fffh ?. ?. ?. ?. ?. ?. ?. ?. 7471 1d2f000h 1d2ffffh 7215 1c2f000h 1c2ffffh ?. ?. ?. ?. ?. ?. 466 7456 1d20000h 1d20fffh 450 7200 1c20000h 1c20fffh 7455 1d1f000h 1d1ffffh 7199 1c1f000h 1c1ffffh ?. ?. ?. ?. ?. ?. 465 7440 1d10000h 1d10fffh 449 7184 1c10000h 1c10fffh 7439 1d0f000h 1d0ffffh 7183 1c0f000h 1c0ffffh ?. ?. ?. ?. ?. ?. 464 7424 1d00000h 1d00fffh 448 7168 1c00000h 1c00fffh
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 8 en25qh256 rev. e, issue date: 2012 / 01/30 table 2. uniform block sector architecture ( 2/8 ) block sector address range block sector address range 7167 1bff000h 1bfffffh 6911 1aff000h 1afffffh ?. ?. ?. ?. ?. ?. 447 7152 1bf0000h 1bf0fffh 431 6896 1af0000h 1af0fffh 7151 1bef000h 1beffffh 6895 1aef000h 1aeffffh ?. ?. ?. ?. ?. ?. 446 7136 1be0000h 1be0fffh 430 6880 1ae0000h 1ae0fffh 7135 1bdf000h 1bdffffh 6879 1adf000h 1adffffh ?. ?. ?. ?. ?. ?. 445 7120 1bd0000h 1bd0fffh 429 6864 1ad0000h 1ad0fffh ?. ?. ?. ?. ?. ?. ?. ?. 6959 1b2f000h 1b2ffffh 6703 1a2f000h 1a2ffffh ?. ?. ?. ?. ?. ?. 434 6944 1b20000h 1b20fffh 418 6688 1a20000h 1a20fffh 6943 1b1f000h 1b1ffffh 6687 1a1f000h 1a1ffffh ?. ?. ?. ?. ?. ?. 433 6928 1b10000h 1b10fffh 417 6672 1a10000h 1a10fffh 6927 1b0f000h 1b0ffffh 6671 1a0f000h 1a0ffffh ?. ?. ?. ?. ?. ?. 432 6912 1b00000h 1b00fffh 416 6656 1a00000h 1a00fffh block sector address range block sector address range 6655 19ff000h 19fffffh 6399 18ff000h 18fffffh ?. ?. ?. ?. ?. ?. 415 6640 19f0000h 19f0fffh 399 6384 18f0000h 18f0fffh 6639 19ef000h 19effffh 6383 18ef000h 18effffh ?. ?. ?. ?. ?. ?. 414 6624 19e0000h 19e0fffh 398 6368 18e0000h 18e0fffh 6623 19df000h 19dffffh 6367 18df000h 18dffffh ?. ?. ?. ?. ?. ?. 413 6608 19d0000h 19d0fffh 397 6352 18d0000h 18d0fffh ?. ?. ?. ?. ?. ?. ?. ?. 6447 192f000h 192ffffh 6191 182f000h 182ffffh ?. ?. ?. ?. ?. ?. 402 6432 1920000h 1920fffh 386 6176 1820000h 1820fffh 6431 191f000h 191ffffh 6175 181f000h 181ffffh ?. ?. ?. ?. ?. ?. 401 6416 1910000h 1910fffh 385 6160 1810000h 1810fffh 6415 190f000h 190ffffh 6159 180f000h 180ffffh ?. ?. ?. ?. ?. ?. 400 6400 1900000h 1900fffh 384 6144 1800000h 1800fffh
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 9 en25qh256 rev. e, issue date: 2012 / 01/30 table 2. uniform block sector architecture ( 3/8 ) block sector address range block sector address range 6143 17ff000h 17fffffh 5887 16ff000h 16fffffh ?. ?. ?. ?. ?. ?. 383 6128 17f0000h 17f0fffh 367 5872 16f0000h 16f0fffh 6127 17ef000h 17effffh 5871 16ef000h 16effffh ?. ?. ?. ?. ?. ?. 382 6112 17e0000h 17e0fffh 366 5856 16e0000h 16e0fffh 6111 17df000h 17dffffh 5855 16df000h 16dffffh ?. ?. ?. ?. ?. ?. 381 6096 17d0000h 17d0fffh 365 5840 16d0000h 16d0fffh ?. ?. ?. ?. ?. ?. ?. ?. 5935 172f000h 172ffffh 5679 162f000h 162ffffh ?. ?. ?. ?. ?. ?. 370 5920 1720000h 1720fffh 354 5664 1620000h 1620fffh 5919 171f000h 171ffffh 5663 161f000h 161ffffh ?. ?. ?. ?. ?. ?. 369 5904 1710000h 1710fffh 353 5648 1610000h 1610fffh 5903 170f000h 170ffffh 5647 160f000h 160ffffh ?. ?. ?. ?. ?. ?. 368 5888 1700000h 1700fffh 352 5632 1600000h 1600fffh block sector address range block sector address range 5631 15ff000h 15fffffh 5375 14ff000h 14fffffh ?. ?. ?. ?. ?. ?. 351 5616 15f0000h 15f0fffh 335 5360 14f0000h 14f0fffh 5615 15ef000h 15effffh 5359 14ef000h 14effffh ?. ?. ?. ?. ?. ?. 350 5600 15e0000h 15e0fffh 334 5344 14e0000h 14e0fffh 5599 15df000h 15dffffh 5343 14df000h 14dffffh ?. ?. ?. ?. ?. ?. 349 5584 15d0000h 15d0fffh 333 5328 14d0000h 14d0fffh ?. ?. ?. ?. ?. ?. ?. ?. 5423 152f000h 152ffffh 5167 142f000h 142ffffh ?. ?. ?. ?. ?. ?. 338 5408 1520000h 1520fffh 322 5152 1420000h 1420fffh 5407 151f000h 151ffffh 5151 141f000h 141ffffh ?. ?. ?. ?. ?. ?. 337 5392 1510000h 1510fffh 321 5136 1410000h 1410fffh 5391 150f000h 150ffffh 5135 140f000h 140ffffh ?. ?. ?. ?. ?. ?. 336 5376 1500000h 1500fffh 320 5120 1400000h 1400fffh
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 10 en25qh256 rev. e, issue date: 2012 / 01/30 table 2. uniform block sector architecture ( 4/8 ) block sector address range block sector address range 5119 13ff000h 13fffffh 4863 12ff000h 12fffffh ?. ?. ?. ?. ?. ?. 319 5104 13f0000h 13f0fffh 303 4848 12f0000h 12f0fffh 5103 13ef000h 13effffh 4847 12ef000h 12effffh ?. ?. ?. ?. ?. ?. 318 5088 13e0000h 13e0fffh 302 4831 12e0000h 12e0fffh 5087 13df000h 13dffffh 4831 12df000h 12dffffh ?. ?. ?. ?. ?. ?. 317 5072 13d0000h 13d0fffh 301 4816 12d0000h 12d0fffh ?. ?. ?. ?. ?. ?. ?. ?. 4911 132f000h 132ffffh 4655 122f000h 122ffffh ?. ?. ?. ?. ?. ?. 306 4896 1320000h 1320fffh 290 4640 1220000h 1220fffh 4895 131f000h 131ffffh 4639 121f000h 121ffffh ?. ?. ?. ?. ?. ?. 305 4880 1310000h 1310fffh 289 4624 1210000h 1210fffh 4879 130f000h 130ffffh 4623 120f000h 120ffffh ?. ?. ?. ?. ?. ?. 304 4864 1300000h 1300fffh 288 4608 1200000h 1200fffh block sector address range block sector address range 4606 11ff000h 11fffffh 4351 10ff000h 10fffffh ?. ?. ?. ?. ?. ?. 287 4592 11f0000h 11f0fffh 271 4336 10f0000h 10f0fffh 4591 11ef000h 11effffh 4335 10ef000h 10effffh ?. ?. ?. ?. ?. ?. 286 4576 11e0000h 11e0fffh 270 4320 10e0000h 10e0fffh 4575 11df000h 11dffffh 4319 10df000h 10dffffh ?. ?. ?. ?. ?. ?. 285 4560 11d0000h 11d0fffh 269 4304 10d0000h 10d0fffh ?. ?. ?. ?. ?. ?. ?. ?. 4399 112f000h 112ffffh 4143 102f000h 102ffffh ?. ?. ?. ?. ?. ?. 274 4384 1120000h 1120fffh 258 4128 1020000h 1020fffh 4383 111f000h 111ffffh 4127 101f000h 101ffffh ?. ?. ?. ?. ?. ?. 273 4368 1110000h 1110fffh 257 4112 1010000h 1010fffh 4367 110f000h 110ffffh 4111 100f000h 100ffffh ?. ?. ?. ?. ?. ?. 272 4353 1100000h 1100fffh 256 4096 1000000h 1000fffh
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 11 en25qh256 rev. e, issue date: 2012 / 01/30 table 2. uniform block sector architecture ( 5/8 ) block sector address range block sector address range 4095 0fff000h 0ffffffh 3839 0eff000h 0efffffh ?. ?. ?. ?. ?. ?. 255 4080 0ff0000h 0ff0fffh 239 3824 0ef0000h 0ef0fffh 4079 0fef000h 0feffffh 3823 0eef000h 0eeffffh ?. ?. ?. ?. ?. ?. 254 4064 0fe0000h 0fe0fffh 238 3808 0ee0000h 0ee0fffh 4063 0fdf000h 0fdffffh 3807 0edf000h 0edffffh ?. ?. ?. ?. ?. ?. 253 4048 0fd0000h 0fd0fffh 237 3792 0ed0000h 0ed0fffh ?. ?. ?. ?. ?. ?. ?. ?. 3887 0f2f000h 0f2ffffh 3631 0e2f000h 0e2ffffh ?. ?. ?. ?. ?. ?. 242 3872 0f20000h 0f20fffh 226 3616 0e20000h 0e20fffh 3871 0f1f000h 0f1ffffh 3615 0e1f000h 0e1ffffh ?. ?. ?. ?. ?. ?. 241 3856 0f10000h 0f10fffh 225 3600 0e10000h 0e10fffh 3855 0f0f000h 0f0ffffh 3599 0e0f000h 0e0ffffh ?. ?. ?. ?. ?. ?. 240 3840 0f00000h 0f00fffh 224 3584 0e00000h 0e00fffh block sector address range block sector address range 3583 0dff000h 0dfffffh 3327 0cff000h 0cfffffh ?. ?. ?. ?. ?. ?. 223 3568 0df0000h 0df0fffh 207 3312 0cf0000h 0cf0fffh 3567 0def000h 0deffffh 3311 0cef000h 0ceffffh ?. ?. ?. ?. ?. ?. 222 3552 0de0000h 0de0fffh 206 3296 0ce0000h 0ce0fffh 3551 0ddf000h 0ddffffh 3295 0cdf000h 0cdffffh ?. ?. ?. ?. ?. ?. 221 3536 0dd0000h 0dd0fffh 205 3280 0cd0000h 0cd0fffh ?. ?. ?. ?. ?. ?. ?. ?. 3375 0d2f000h 0d2ffffh 3119 0c2f000h 0c2ffffh ?. ?. ?. ?. ?. ?. 210 3360 0d20000h 0d20fffh 194 3014 0c20000h 0c20fffh 3359 0d1f000h 0d1ffffh 3103 0c1f000h 0c1ffffh ?. ?. ?. ?. ?. ?. 209 3344 0d10000h 0d10fffh 193 3088 0c10000h 0c10fffh 3343 0d0f000h 0d0ffffh 3087 0c0f000h 0c0ffffh ?. ?. ?. ?. ?. ?. 208 3328 0d00000h 0d00fffh 192 3072 0c00000h 0c00fffh
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 12 en25qh256 rev. e, issue date: 2012 / 01/30 table 2. uniform block sector architecture ( 6/8) block sector address range block sector address range 3071 0bff000h 0bfffffh 2815 0aff000h 0afffffh ?. ?. ?. ?. ?. ?. 191 3056 0bf0000h 0bf0fffh 175 2800 0af0000h 0af0fffh 3055 0bef000h 0beffffh 2799 0aef000h 0aeffffh ?. ?. ?. ?. ?. ?. 190 3040 0be0000h 0be0fffh 174 2784 0ae0000h 0ae0fffh 3039 0bdf000h 0bdffffh 2783 0adf000h 0adffffh ?. ?. ?. ?. ?. ?. 189 3024 0bd0000h 0bd0fffh 173 2768 0ad0000h 0ad0fffh ?. ?. ?. ?. ?. ?. ?. ?. 2863 0b2f000h 0b2ffffh 2607 0a2f000h 0a2ffffh ?. ?. ?. ?. ?. ?. 178 2848 0b20000h 0b20fffh 162 2592 0a20000h 0a20fffh 2847 0b1f000h 0b1ffffh 2591 0a1f000h 0a1ffffh ?. ?. ?. ?. ?. ?. 177 2832 0b10000h 0b10fffh 161 2576 0a10000h 0a10fffh 2831 0b0f000h 0b0ffffh 2575 0a0f000h 0a0ffffh ?. ?. ?. ?. ?. ?. 176 2816 0b00000h 0b00fffh 160 2560 0a00000h 0a00fffh block sector address range block sector address range 2559 09ff000h 09fffffh 2303 08ff000h 08fffffh ?. ?. ?. ?. ?. ?. 159 2544 09f0000h 09f0fffh 143 2288 08f0000h 08f0fffh 2543 09ef000h 09effffh 2287 08ef000h 08effffh ?. ?. ?. ?. ?. ?. 158 2528 09e0000h 09e0fffh 142 2272 08e0000h 08e0fffh 2527 09df000h 09dffffh 2271 08df000h 08dffffh ?. ?. ?. ?. ?. ?. 157 2512 09d0000h 09d0fffh 141 2256 08d0000h 08d0fffh ?. ?. ?. ?. ?. ?. ?. ?. 2351 092f000h 092ffffh 2095 082f000h 082ffffh ?. ?. ?. ?. ?. ?. 146 2336 0920000h 0920fffh 130 2080 0820000h 0820fffh 2335 091f000h 091ffffh 2079 081f000h 081ffffh ?. ?. ?. ?. ?. ?. 145 2320 0910000h 0910fffh 129 2064 0810000h 0810fffh 2319 090f000h 090ffffh 2063 080f000h 080ffffh ?. ?. ?. ?. ?. ?. 144 2304 0900000h 0900fffh 128 2048 0800000h 0800fffh
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 13 en25qh256 rev. e, issue date: 2012 / 01/30 table 2. uniform block sector architecture ( 7/8 ) block sector address range block sector address range 2047 07ff000h 07fffffh 1791 06ff000h 06fffffh ?. ?. ?. ?. ?. ?. 127 2032 07f0000h 07f0fffh 111 1776 06f0000h 06f0fffh 2031 07ef000h 07effffh 1775 06ef000h 06effffh ?. ?. ?. ?. ?. ?. 126 2016 07e0000h 07e0fffh 110 1760 06e0000h 06e0fffh 2015 07df000h 07dffffh 1759 06df000h 06dffffh ?. ?. ?. ?. ?. ?. 125 2000 07d0000h 07d0fffh 109 1744 06d0000h 06d0fffh ?. ?. ?. ?. ?. ?. ?. ?. 1839 072f000h 072ffffh 1583 062f000h 062ffffh ?. ?. ?. ?. ?. ?. 114 1824 0720000h 0720fffh 98 1568 0620000h 0620fffh 1823 071f000h 071ffffh 1567 061f000h 061ffffh ?. ?. ?. ?. ?. ?. 113 1808 0710000h 0710fffh 97 1552 0610000h 0610fffh 1807 070f000h 070ffffh 1551 060f000h 060ffffh ?. ?. ?. ?. ?. ?. 112 1972 0700000h 0700fffh 96 1536 0600000h 0600fffh block sector address range block sector address range 1535 05ff000h 05fffffh 1279 04ff000h 04fffffh ?. ?. ?. ?. ?. ?. 95 1520 05f0000h 05f0fffh 79 1264 04f0000h 04f0fffh 1519 05ef000h 05effffh 1263 04ef000h 04effffh ?. ?. ?. ?. ?. ?. 94 1504 05e0000h 05e0fffh 78 1248 04e0000h 04e0fffh 1503 05df000h 05dffffh 1247 04df000h 04dffffh ?. ?. ?. ?. ?. ?. 93 1488 05d0000h 05d0fffh 77 1232 04d0000h 04d0fffh ?. ?. ?. ?. ?. ?. ?. ?. 1327 052f000h 052ffffh 1071 042f000h 042ffffh ?. ?. ?. ?. ?. ?. 82 1312 0520000h 0520fffh 66 1056 0420000h 0420fffh 1311 051f000h 051ffffh 1055 041f000h 041ffffh ?. ?. ?. ?. ?. ?. 81 1296 0510000h 0510fffh 65 1040 0410000h 0410fffh 1295 050f000h 050ffffh 1039 040f000h 040ffffh ?. ?. ?. ?. ?. ?. 80 1280 0500000h 0500fffh 64 1024 0400000h 0400fffh
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 14 en25qh256 rev. e, issue date: 2012 / 01/30 table 2. uniform block sector architecture ( 8/8 ) block sector address range block sector address range 1023 03ff000h 03fffffh 767 02ff000h 02fffffh ?. ?. ?. ?. ?. ?. 63 1008 03f0000h 03f0fffh 47 752 02f0000h 02f0fffh 1007 03ef000h 03effffh 751 02ef000h 02effffh ?. ?. ?. ?. ?. ?. 62 992 03e0000h 03e0fffh 46 736 02e0000h 02e0fffh 991 03df000h 03dffffh 735 02df000h 02dffffh ?. ?. ?. ?. ?. ?. 61 976 03d0000h 03d0fffh 45 720 02d0000h 02d0fffh ?. ?. ?. ?. ?. ?. ?. ?. 815 032f000h 032ffffh 559 022f000h 022ffffh ?. ?. ?. ?. ?. ?. 50 800 0320000h 0320fffh 34 544 0220000h 0220fffh 799 031f000h 031ffffh 543 021f000h 021ffffh ?. ?. ?. ?. ?. ?. 49 784 0310000h 0310fffh 33 528 0210000h 0210fffh 783 030f000h 030ffffh 527 020f000h 020ffffh ?. ?. ?. ?. ?. ?. 48 768 0300000h 0300fffh 32 512 0200000h 0200fffh block sector address range block sector address range 511 01ff000h 01fffffh 255 00ff000h 00fffffh ?. ?. ?. ?. ?. ?. 31 496 01f0000h 01f0fffh 15 240 00f0000h 00f0fffh 495 01ef000h 01effffh 239 00ef000h 00effffh ?. ?. ?. ?. ?. ?. 30 480 01e0000h 01e0fffh 14 224 00e0000h 00e0fffh 479 01df000h 01dffffh 223 00df000h 00dffffh ?. ?. ?. ?. ?. ?. 29 464 01d0000h 01d0fffh 13 208 00d0000h 00d0fffh ?. ?. ?. ?. ?. ?. ?. ?. 303 012f000h 012ffffh 47 002f000h 002ffffh ?. ?. ?. ?. ?. ?. 18 288 0120000h 0120fffh 2 32 0020000h 0020fffh 287 011f000h 011ffffh 31 001f000h 001ffffh ?. ?. ?. ?. ?. ?. 17 272 0110000h 0110fffh 1 16 0010000h 0010fffh 271 010f000h 010ffffh 15 000f000h 000ffffh ?. ?. ?. ?. ?. ?. 16 256 0100000h 0100fffh 4 0004000h 0004fffh 3 0003000h 0003fffh 2 0002000h 0002fffh 1 0001000h 0001fffh 0 0 0000000h 0000fffh
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 15 en25qh256 rev. e, issue date: 2012 / 01/30 operating features standard spi modes the en25qh256 is accessed through a spi compatible bus consisting of four signals: serial clock (clk), chip select (cs#), serial data input (di) and serial data output (do). both spi bus operation modes 0 (0,0) and 3 (1,1) are supported. the primary difference between mode 0 and mode 3, as shown in figure 3, concerns the normal state of the clk signal when the spi bus master is in standby and data is not being transferred to the serial flash. for mode 0 the clk signal is normally low. for mode 3 the clk signal is normally high. in either case data input on the di pin is sampled on the rising edge of the clk. data output on the do pi n is clocked out on the falling edge of clk. figure 3. spi modes dual spi instruction the en25qh256 supports dual spi operation when using the ?dual output fast read and dual i/o fast read ? (3bh and bbh) instructions. these instructions allow data to be transferred to or from the serial flash memory at two to three times the rate possible with the standard spi. the dual read instructions are ideal for quickly downloading code from flash to ram upon power-up (code-shadowing) or for application that cache code-segments to ram for execution. the dual output feature simply allows the spi input pin to also serve as an output during this instruction. when using dual spi instructions the di and do pins become bidirectional i/o pins; dq 0 and dq 1 . all other operations use the standard spi interface with single output signal. quad spi instruction the en25qh256 supports quad output operation when using the quad i/o fast read (ebh).this instruction allows data to be transferred to or from the serial flash memory at four to six times the rate possible with the standard spi. the quad read instruction offer a significant improvement in continuous and random access transfer rates allowing fast code-shadowing to ram or for application that cache code-segments to ram for execution. the en25qh256 also supports full quad mode function while using the enable quad peripheral interface mode (eqpi) (38h). when using quad spi instruction the di and do pins become bidirectional i/o pins; dq 0 and dq 1, and the wp# and hold# pins become dq 2 and dq 3 respectively.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 16 en25qh256 rev. e, issue date: 2012 / 01/30 figure 4. quad spi modes note: please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. page programming to program one data byte, two instructions are required: write enable (wren), which is one byte, and a page program (pp) sequence, which consists of four bytes plus data. this is followed by the internal program cycle (of duration t pp ). to spread this overhead, the page program (pp) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0) provided that they lie in consecutive addresses on the same page of memory. sector erase, block erase and chip erase the page program (pp) instruction allows bits to be reset from 1 to 0. before this can be applied, the bytes of memory need to have been erased to all 1s (ffh). this can be achieved a sector at a time, using the sector erase (se) instruction, a block at a time using the block erase (be) instruction or throughout the entire memory, using the chip erase (ce) instruction. this starts an internal erase cycle (of duration t se t be or t ce ). the erase instruction must be preceded by a write enable (wren) instruction. polling during a write, program or erase cycle a further improvement in the time to write status register (wrsr), program (pp) or erase (se, be or ce) can be achieved by not waiting for the worst case delay (t w , t pp , t se , t be or t ce ). the write in progress (wip) bit is provided in the status register so that the application program can monitor its value, polling it to estab lish when the previous write cycle, prog ram cycle or erase cycle is complete. active power, stand-by power and deep power-down modes when chip select (cs#) is low, the device is enabled, and in the active power mode. when chip select (cs#) is high, the device is disabled, but could remain in the active power mode until all internal cycles have completed (program, erase, and write status register). the device then goes into the stand-by power mode. the device consumption drops to i cc1 . the deep power-down mode is entered when the specific instruction (the enter deep power-down mode (dp) instruction) is executed. the device consumption drops further to i cc2 . the device remains in this mode until another specif ic instruction (the release from deep power-down mode and read device id (rdi) instruction) is executed.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 17 en25qh256 rev. e, issue date: 2012 / 01/30 all other instructions are ignored while the device is in the deep power-down mode. this can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent write, program or erase instructions. status register and information register the status register and information register contain a number of status and control bits that can be read or set (as a ppropriate) by specific instructions. wip bit. the write in progress (wip) bit indicates whethe r the memory is busy with a write status register, program or erase cycle. wel bit. the write enable latch (wel) bit indicates the status of the internal write enable latch. bp3, bp2, bp1, bp0 bits. the block protect (bp3, bp2, bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against program and erase instructions. qe bit. the quad enable (qe) bit, non-volatile bit, enable bit only for quad input/output fast_read (ebh) in spi command. when it is ?0? (factory default), it disables quad input/output fast_read (ebh) in spi command and wp#, hold# are enabled. while qe is ?1?, it enables quad input/output fast_read (ebh) in spi command and wp#, hold# are disabled. in other words, in spi mode, the qe bit needs to be assigned through wrsr to enable or disable spi command quad input/output fast_read (ebh). if the system goes into full quad i/o (eqpi), this qe bit becomes no affection since wp# and hold# function will be disabled by eqpi mode and quad input/output fast_read (ebh) will be always ava ilable in eq pi mode. srp bit / otp_lock bit the status register protect (srp) bit operates in conjunction with the write protect (wp#) signal. the status register protect (srp) bit and write protect (wp#) signal allow the device to be put in the hardware protected mode. in this mode, the non-volatile bits of the status register (srp, bp3, bp2, bp1, bp0) become read-only bits. in otp mode, this bit serves as otp_lock bit, user can read/program/erase otp sector as normal sector while otp_lock bit value is equal 0, after otp_lock bit is programmed with 1 by wrsr command, the otp sector is protected from program and erase operation. the otp_lock bit can only be programmed once. note : in otp mode, the wrsr command will ignore any input data and program otp_lock bit to 1, user must clear the protect bits before entering otp mode and program the otp code, then execute wrsr command to lock the otp sector before leaving otp mode. 4 byte indicator bit. by writing en4b instruction, the 4 byte bit may be set to ?1? to access the address length of 32-bit for higher density (larger than 128mb) memory area. the default state is ?0?, which means the mode of 24-bit address. the 4 byte bit may be clear by power off or writing ex4b instruction to reset the state to be ?0? program fail flag bit. while a program failure happened, the program fail flag bit would be set. this bit will also be set when the user attempts to program a protected main memory region or a locked otp region. this bit can indicate whether one or more of program operations fail, and can be reset by program (pp) or erase (se, be or ce) instructions. erase fail flag bit. while an erase failure happened, the eras e fail flag bit would be set. this bit will also be set when the user attempts to erase a protected main memory region or a locked otp region. this bit can indicate whether one or more of erase operations fail, and can be reset by program (pp) or erase (se, be or ce) instructions. note : for program and erase flag bits, 1. the flag bits can be reset by power-on or that embedded mode was executed like wrsr, erase or program command. 2. if the system is trying to erase a locked block and then program a locked block. the erase fail or program fail flag bit will be high due to no su ccessful program, erase or wrse command.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 18 en25qh256 rev. e, issue date: 2012 / 01/30 write protection applications that use non-volatile me mory must take into consideratio n the possibility of noise and other adverse system conditions that may compromise data integrity. to address this concern the en25qh256 provides the following data protection mechanisms: z power-on reset and an internal timer (t puw ) can provide protection against inadvertent changes while the power supply is outside the operating specification. z program, erase and write status register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. z all instructions that modify data must be preceded by a write enable (wren) instruction to set the write enable latch (wel) bit. this bit is returned to its reset state by the following events: ? power-up ? write disable (wrdi) instruction completion or write status register (wrsr) instruction completion or page program (pp) instruction completion or sector erase (se) instruction completion or block erase (be) instruction completion or chip erase (ce) instruction completion z the block protect (bp3, bp2, bp1, bp0) bits allow part of the memory to be configured as read- only. this is the software protected mode (spm). z the write protect (wp#) signal allows the block protect (bp3, bp2, bp1, bp0) bits and status register protect (srp) bit to be protected. this is the hardware protected mode (hpm). z in addition to the low power consumption feature, the deep power-down mode offers extra software protection from inadvertent write, program and erase instructions, as all instructions are ignored except one particular instruction (the release from deep power-down instruction). table 3. protected area sizes sector organization status register content memory content bp3 bit bp2 bit bp1 bit bp0 bit protect areas addresses density(kb) portion 0 0 0 0 none none none none 0 0 0 1 block 511 1ff0000h-1ffffffh 64kb upper 1/512 0 0 1 0 block 510 to 511 1fe0000h-1ffffffh 128kb upper 2/512 0 0 1 1 block 508 to 511 1fc0000h-1ffffffh 256kb upper 4/512 0 1 0 0 block 504 to 511 1f80000h-1ffffffh 512kb upper 8/512 0 1 0 1 block 496 to 511 1f00000h-1ffffffh 1024kb upper 16/512 0 1 1 0 block 480 to 511 1e00000h-1ffffffh 2048kb upper 32/512 0 1 1 1 all 0000000h-1ffffffh 32768kb all 1 0 0 0 none none none none 1 0 0 1 block 0 0000000h-000ffffh 64kb lower 1/512 1 0 1 0 block 0 to 1 0000000h-001ffffh 128kb lower 2/512 1 0 1 1 block 0 to 3 0000000h-003ffffh 256kb lower 4/512 1 1 0 0 block 0 to 7 0000000h-007ffffh 512kb lower 8/512 1 1 0 1 block 0 to 15 0000000h-00fffffh 1024kb lower 16/512 1 1 1 0 block 0 to 31 0000000h-01fffffh 2048kb lower 32/512 1 1 1 1 all 0000000h-1ffffffh 32768kb all
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 19 en25qh256 rev. e, issue date: 2012 / 01/30 instructions all instructions, addresses and data are shifted in and out of the device, most significant bit first. serial data input (di) is sampled on the first rising edge of serial clock (clk) after chip select (cs#) is driven low. then, the one-byte instruction code must be shifted in to the device, most significant bit first, on serial data input (di), each bit being latched on the rising edges of serial clock (clk). the instruction set is listed in tabl e 4. every instruction sequence st arts with a one-byte instruction code. depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. chip select (cs#) must be driven high after the last bit of the instruction sequence has been shifted in. in the case of a read data bytes (read), read data bytes at higher speed (fast_read), dual output fast read (3bh), dual i/o fast read (bbh), quad input/output fast_read (ebh), read status register (rdsr), read information register (rdifr) or release from deep power-down, and read device id (rdi) in struction, the shifted-in instruction sequence is followed by a data-out sequence. chip select (cs#) can be driven high after any bit of the data-out sequence is being shifted out. in the case of a page program (pp), sector erase (se), block erase (be), chip erase (ce), write status register (wrsr), write enable (wren), write disable (wrdi) or deep power-down (dp) instruction, chip select (cs#) must be driven high exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. that is, chip select (cs#) must driven high when the number of clock pulses after chip select (cs#) being driven low is an exact multiple of eight. for page program, if at any time the input byte is not a full byte, no thing will happen and we l will not be reset. in the case of multi-byte commands of page program (pp), and release from deep power down (res ) minimum number of bytes specified has to be given, without which, the command will be ignored. in the case of page program, if the number of byte after the command is less than 4 (at least 1 data byte), it will be ignored too. in the case of se and be, exact 24-bit address is a must, any less or more will cause the command to be ignored. all attempts to access the memory array during a writ e status register cycle, program cycle or erase cycle are ignored, and the internal write status register cycle, program cycle or erase cycle continues unaffected.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 20 en25qh256 rev. e, issue date: 2012 / 01/30 table 4a. instruction set instruction name byte 1 code byte 2 byte 3 byte 4 byte 5 byte 6 n-bytes eqpi 38h rstqio (2) ffh rsten 66h rst (1) 99h write enable 06h write disable / exit otp mode 04h read status register 05h (s7-s0) (3) continuous (4) read information register 2bh (s7-s0) (3) continuous (4) write status register 01h s7-s0 enter 4-byte mode b7h exit 4-byte mode e9h enter high bank latch mode 67h exit high bank latch mode 98h page program 02h (8) a23-a16 a15-a8 a7-a0 d7-d0 next byte continuous sector erase 20h (8) a23-a16 a15-a8 a7-a0 block erase d8h (8) a23-a16 a15-a8 a7-a0 chip erase c7h/ 60h deep power-down b9h release from deep power-down, and read device id dummy dummy dummy (id7-id0) (5) release from deep power-down abh 00h (m7-m0) (id7-id0) manufacturer/ device id 90h dummy dummy 01h (id7-id0) (m7-m0) (6) read identification 9fh (m7-m0) (id15-id8) (id7-id0) (7) enter otp mode 3ah read sfdp mode and unique id number 5ah (8) a23-a16 a15-a8 a7-a0 dummy (d7-d0) (next byte) continuous notes: 1. rst command only executed if rsten command is executed first. any intervening command will disable reset. 2. device accepts eight-clocks command in standard spi mode, or two-clocks command in quad spi mode 3. data bytes are shifted with most significant bit first. byte fields with data in parenthesis ?( )? indicate data being read from the device on the do pin 4. the status register contents will repeat continuously until cs# terminate the instruction 5. the device id will repeat continuously until cs# terminates the instruction 6. the manufacturer id and device id bytes will repeat continuously until cs# terminates the instruction. 00h on byte 4 starts with mid and alternate with did, 01h on byte 4 starts with did and alternate with mid 7. (m7-m0) : manufacturer, (id15-id8) : memory type, (id7-id0) : memory capacity 8. please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 21 en25qh256 rev. e, issue date: 2012 / 01/30 table 4b. instruction set (read instruction) instruction name byte 1 code byte 2 byte 3 byte 4 byte 5 byte 6 n-bytes read data 03h (6) a23-a16 a15-a8 a7-a0 (d7-d0) (next byte) continuous fast read 0bh (6) a23-a16 a15-a8 a7-a0 dummy (d7-d0) (next byte) continuous dual output fast read 3bh (6) a23-a16 a15-a8 a7-a0 dummy (d7-d0, ?) (1) (one byte per 4 clocks, continuous) dual i/o fast read bbh (6) a23-a8 (2) a7-a0, dummy (2) (d7-d0, ?) (1) (one byte per 4 clocks, continuous) quad i/o fast read ebh (6) a23-a0, dummy (4) ( dummy , d7-d0 ) (5) (d7-d0, ?) (3) (one byte per 2 clocks, continuous) notes: 1. dual output data dq 0 = (d6, d4, d2, d0) dq 1 = (d7, d5, d3, d1) 2. dual input address dq 0 = a22, a20, a18, a16, a14, a12, a10, a8 ; a6, a4, a2, a0, dummy 6, dummy 4, dummy 2, dummy 0 dq 1 = a23, a21, a19, a17, a15, a13, a11, a9 ; a7, a5, a3, a1, dummy 7, dummy 5, dummy 3, dummy 1 3. quad data dq 0 = (d4, d0, ?? ) dq 1 = (d5, d1, ?? ) dq 2 = (d6, d2, ?... ) dq 3 = (d7, d3, ?... ) 4. quad input address dq 0 = a20, a16, a12, a8, a4, a0, dummy 4, dummy 0 dq 1 = a21, a17, a13, a9, a5, a1, dummy 5, dummy 1 dq 2 = a22, a18, a14, a10, a6, a2, dummy 6, dummy 2 dq 3 = a23, a19, a15, a11, a7, a3, dummy 7, dummy 3 5. quad i/o fast read data dq 0 = ( dummy 12, dummy 8, dummy 4, dummy 0, d4, d0 ) dq 1 = ( dummy 13, dummy 9, dummy 5, dummy 1, d5, d1 ) dq 2 = ( dummy 14, dummy 10, dummy 6, dummy 2, d6, d2 ) dq 3 = ( dummy 15, dummy 11, dummy 7, dummy 3, d7, d3 ) 6. please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 22 en25qh256 rev. e, issue date: 2012 / 01/30 table 5. manufacturer and device identification op code (m7-m0) (id15-id0) (id7-id0) abh 18h 90h 1ch 18h 9fh 1ch 7019h enable quad peripheral interface mode (eqpi) (38h) the enable quad peripheral interface mode (eqpi) instruction will enable the flash device for quad spi bus operation. upon completion of the instruction, all instru ctions thereafter will be 4-bit multiplexed input/output until a power cycle or ? reset quad i/o instruction ? instruction, as shown in figure 5. the device did not support the read data bytes (read) (03h) , dual output fast read (3bh) and dual input/output fast_read (bbh) modes while the enable quad peripheral interface mode (eqpi) (38h) turns on. figure 5. enable quad peripheral interface mode sequence diagram reset quad i/o (rstqio) (ffh) the reset quad i/o instruction resets the device to 1-bit standard spi operation. to execute a reset quad i/o operation, the host drives cs# low, sends the reset quad i/o command cycle (ffh) then, drives cs# high. this command can?t be used in standard spi mode.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 23 en25qh256 rev. e, issue date: 2012 / 01/30 reset-enable (rsten) (66h) and reset (rst) (99h) the reset operation is used as a system (software) reset that puts the device in normal operating ready mode. this operation consists of two commands: reset-enable (rsten) and reset (rst). to reset the en25qh256 the host drives cs# low, sends the reset-enable command (66h), and drives cs# high. next, the host drives cs# low again, sends the reset command (99h), and drives cs# high. the reset operation requires the reset-enable command followed by the reset command. any command other than the reset command after the reset-enable command will disable the reset- enable. a successful command execution will re set the status register and the information register to data = 00h, see figure 6 for spi mode and figure 6.1 for eqpi mode. a device reset during an active program or erase operation aborts the operation, which can cause the data of the targeted address range to be corrupted or lost. depending on the prior operation, the reset timing may vary. recovery from a write operation requires more software latency time (t sr ) than recovery from other operations. figure 6. reset-enable and reset sequence diagram figure 6.1 reset-enable and reset sequence diagram under eqpi mode
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 24 en25qh256 rev. e, issue date: 2012 / 01/30 software reset flow initial command = 66h ? reset enable command = 99h ? reset start wip = 0 ? reset done embedded reset cycle yes no no yes no yes note: 1. reset-enable (rsten) (66h) and reset (rst) (99h) commands need to match standard spi or eqpi (quad) mode. 2. continue (enhance) eb mode need to use quad reset-enable (rsten) (66h) and quad reset (rst) (99h) commands. 3. if user is not sure it is in spi or quad mode, we suggest to execute sequence as follows: quad reset-enable (rsten) (66h) -> quad reset (rst) (99h) -> spi reset-enable (rsten) (66h) -> spi reset (rst) (99h) to reset. 4. the reset command could be executed during embedded program and erase process, eqpi mode and continue eb mode to back to spi mode. 5. this flow cannot release the device from deep power down mode. 6. the status register bit and information register bit will reset to default value after reset done. 7. if user reset device during erase, the embedded reset cycle software reset latency will take about 28us in worst case.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 25 en25qh256 rev. e, issue date: 2012 / 01/30 write enable (wren) (06h) the write enable (wren) instruction (figure 7) sets the write enable latch (wel) bit. the write enable latch (wel) bit must be set prior to every page program (pp), sector erase (se), block erase (be), chip erase (ce) and write status register (wrsr) instruction. the write enable (wren) instruction is entered by driving chip select (cs#) low, sending the instruction code, and then driving chip select (cs#) high. the instruction sequence is shown in figure 8.1 while using the enable quad peripheral interface mode (eqpi) (38h) command. figure 7. write enable instruction sequence diagram write disable (wrdi) (04h) the write disable instruction (figure 8) resets the write enable latch (wel) bit in the status register to a 0 or exit from otp mode to normal mode. the write disable instruction is entered by driving chip select (cs#) low, shifting the instruction code ?04h? into the di pin and then driving chip select (cs#) high. note that the wel bit is automatically reset after power-up and upon completion of the write status register, page program, sector erase, block erase (be) and chip erase instructions. the instruction sequence is shown in figure 8.1 while using the enable quad peripheral interface mode (eqpi) (38h) command. figure 8. write disable instruction sequence diagram
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 26 en25qh256 rev. e, issue date: 2012 / 01/30 figure 8.1 write enable/disable instruction sequence under eqpi mode read status register (rdsr) (05h) the read status register (rdsr) instruction allows the status register to be read. the status register may be read at any time, even while a program, erase or write status register cycle is in progress. when one of these cycles is in progress, it is recommended to check the write in progress (wip) bit before sending a new instruction to the device. it is also possible to read the status register continuously, as shown in figure 9. the instruction sequence is shown in figure 9.1 while using the enable quad peripheral interface mode (eqpi) (38h) command. figure 9. read status register instruction sequence diagram
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 27 en25qh256 rev. e, issue date: 2012 / 01/30 figure 9.1 read status register instruction sequence under eqpi mode table 6. status register bit locations s7 s6 s5 s4 s3 s2 s1 s0 srp status register protect otp_lock bit (note 1) qe (quad enable) bp3 (block protected bits) bp2 (block protected bits) bp1 (block protected bits) bp0 (block protected bits) wel (write enable latch) wip (write in progress bit) (note 3) 1 = status register write disable 1 = otp sector is protected 1 = quad enable 0 = not quad enable (note 2) (note 2) (note 2) (note 2) 1 = write enable 0 = not write enable 1 = write operation 0 = not in write operation non-volatile bit non-volatile bit non-volatile bit. non-volatile bit non-volatile bit non-volatile bit volatile bit volatile bit note 1. in otp mode, srp bit is served as otp_lock bit. 2. see the table ? protected area sizes sector organization?. 3. when executed the (rdsr) (05h) command, the otp_lock bit (s7 / in otp mode) value is the same as otp_lock bit (s1) in table 7. the status and control bits of the status register are as follows: wip bit. the write in progress (wip) bit indicates whether the memory is busy with a write status register, program or erase cycle. when set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. wel bit. the write enable latch (wel) bit indicates the status of the internal write enable latch. when set to 1 the internal write enable latch is set, when set to 0 the internal write enable latch is reset and no write status register, program or erase instruction is accepted. bp3, bp2, bp1, bp0 bits. the block protect (bp3, bp2, bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against program and erase instructions. these bits are written with the write status register (wrsr) instruction. when one or both of the block protect (bp3, bp2, bp1, bp0) bits is set to 1, the relevant memory area (as defined in table 3.) becomes protected against page program (pp) sector erase (se) and , block erase (be), instructions. the block protect
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 28 en25qh256 rev. e, issue date: 2012 / 01/30 (bp3, bp2, bp1, bp0) bits can be written provided that the hardware protected mode has not been set. the chip erase (ce) instruction is executed if, and only if, all block protect (bp3, bp2, bp1, bp0) bits are 0. qe bit. the quad enable (qe) bit, non-volatile bit, enable bit only for quad input/output fast_read (ebh) in spi command. when it is ?0? (factory default), it disables quad input/output fast_read (ebh) in spi command and wp#, hold# are enabled. while qe is ?1?, it enables quad input/output fast_read (ebh) in spi command and wp#, hold# are disabled. in other words, in spi mode, the qe bit needs to be assigned through wrsr to enable or disable spi command quad input/output fast_read (ebh). if the system goes into full quad i/o (eqpi), this qe bit becomes no affection since wp# and hold# function will be disabled by eqpi mode and quad input/output fast_read (ebh) will be always available in eqpi mode. srp bit / otp_lock bit. the status register protect (srp) bit operates in conjunction with the write protect (wp#) signal. the status register write protect (srp) bit and write protect (wp#) signal allow the device to be put in the hardware protected mode (when the status register protect (srp) bit is set to 1, and write protect (wp#) is driven low). in this mode, the non-volatile bits of the status register (srp, bp3, bp2, bp1, bp0) become read-only bits and the write status register (wrsr) instruction is no longer accepted for execution. in otp mode, this bit serves as otp_lock bit, user can read/program/erase otp sector as normal sector while otp_lock bit value is equal 0, after otp_lock bit is programmed with 1 by wrsr command, the otp sector is protected from program and erase operation. the otp_lock bit can only be programmed once. note : in otp mode, the wrsr command will ignore any input data and program otp_lock bit to 1, user must clear the protect bits before enter otp mode and program the otp code, then execute wrsr command to lock the otp sector before leaving otp mode. read information register (rdifr) (2bh) the read information register (rdifr) instruction is for reading the value of information register. the read information register can be read at any time (even in program/erase/write status register condition) and continuously, as shown in figure 10. the sequence of issuing rdifr instruction is: cs# goes low -> sending rdifr instruction -> information register data out on do -> cs# goes high. the instruction sequence is shown in figure 10.1 while using the enable quad peripheral interface mode (eqpi) (38h) command. figure 10. read information register instruction sequence diagram
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 29 en25qh256 rev. e, issue date: 2012 / 01/30 figure 10.1 read information register instruction sequence under eqpi mode table 7. information register bit locations s7 s6 s5 s4 s3 s2 s1 s0 hbl (high bank latch bit) erase fail flag program fail flag 4 byte otp_lock bit 1 = access larger than 128mb 0 = access smaller than 128mb (default = 0) 1 = indicate erase failed 0 = normal erase succeed (default = 0) 1 = indicate program failed 0 = normal program succeed (default = 0) 1 = 4-byte address mode 0 = 3-byte address mode (default = 0) 1 = otp sector is protected volatile bit volatile bit volatile bit volatile bit non-volatile bit read only read only read only reserved bit reserved bit read only read only reserved bit note: 1. when executed the (rdifr) (2bh) command, the otp_lock bit (s1) value is the same as otp_lock bit (s7 / in otp mode) in table 6. 2. default at power-up is ?0?
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 30 en25qh256 rev. e, issue date: 2012 / 01/30 the status and control bits of the secured register are as follows: reserved bit. information register bit locations 0, 3 and 4 are reserved for future use. current devices will read 0 for these bit locations. it is recommended to mask out the reserved bit when testing the suspend status register. doing this will ensure compatibility with future devices. otp_lock bit. the otp_lock bit, user can read/program/erase otp sector as normal sector while otp_lock bit value is equal 0, after otp_lock bit is programmed with 1 by wrsr command, the otp sector is protected from program and erase operation. the otp_lock bit can only be programmed once. 4 byte indicator bit. by writing en4b instruction, the 4 byte bit may be set to ?1? to access the address length of 32-bit for higher density (large than 128mb) memory area. the default state is ?0?, which means the mode of 24-bit address. the 4 byte bit may be clear by power off or writing ex4b instruction to reset the state to be ?0? program fail flag bit. while a program failure happened, the program fail flag bit would be set. this bit will also be set when the user attempts to program a protected main memory region or a locked otp region. this bit can indicate whether one or more of program operations fail, and can be reset by program (pp) or erase (se, be or ce) instructions. erase fail flag bit. while an erase failure happened, the erase fail flag bit would be set. this bit will also be set when the user attempts to erase a protected main memory region or a locked otp region. this bit can indicate whether one or more of erase operations fail, and can be reset by program (pp) or erase (se, be or ce) instructions. note : for program and erase flag bits, 1. the flag bits can be reset by power-on or that embedded mode was executed like wrsr, erase or program command. 2. if the system is trying to erase a locked block and then program a locked block. the erase fail or program fail flag bit will be high due to no successful program, erase or wrse command. hbl bit. the high bank latch (hbl) bit indicates the status of the internal high bank latch. by writing enhb instruction, the hbl bit may be set to ?1? to access the memory area of higher bank (larger than 128m). the default state is ?0?, which mean if execute read / program / erase command, then the first byte addresses will be accessed at the memory area of lower density (smaller than 128m). the hbl bit may be clear by power off or writing exhbl instruction to reset the state to be ?0? write status register (wrsr) (01h) the write status register (wrsr) instruction allows new values to be written to the status register. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded and executed, the device sets the write enable latch (wel). the write status register (wrsr) instruction is entered by driving chip select (cs#) low, followed by the instruction code and the data byte on serial data input (di). the instruction sequence is shown in figure 11. the write status register (wrsr) instruction has no effect on s1 and s0 of the status register. chip select (cs#) must be driven high after the eighth bit of the data byte has been latched in. if not, the write status register (wrsr) instruction is not executed. as soon as chip select (cs#) is driven high, the self-timed write status register cycle (whose duration is t w ) is initiated. while the write status register cycle is in progress, the status register may still be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed write status register cycle, and is 0 when it is completed. when the cycle is completed, the write enable latch (wel) is reset. the write status register (wrsr) instruction allows the user to change the values of the block protect (bp3, bp2, bp1, bp0) bits, to define the size of the area that is to be treated as read-only, as defined in table 3. the write status register (wrsr) instruction also allows the user to set or reset the status register protect (srp) bit in accordance with the write protect (wp#) signal. the status register protect (srp) bit and write protect (wp#) signal allow the device to be put in the hardware protected mode (hpm). the write status register (wrsr) instruction is not executed once the hardware protected mode (hpm) is entered.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 31 en25qh256 rev. e, issue date: 2012 / 01/30 the instruction sequence is shown in figure 11.1 while using the enable quad peripheral interface mode (eqpi) (38h) command. note : in the otp mode, wrsr command will igno re input data and program otp_lock bit to 1. figure 11. write status register instruction sequence diagram figure 11.1 write status register instruction sequence under eqpi mode
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 32 en25qh256 rev. e, issue date: 2012 / 01/30 enter 4-byte mode (en4b) (b7h) the en4b instruction enables accessing the address length of 32-bit for the memory area of higher density (larger than 128mb). the device default is in 24-bit address mode; after sending out the en4b instruction, the bit 2 (4 byte bit) of information register will be automatically set to ?1? to indicate the 4- byte address mode has been enabled. once the 4-byte address mode is enable, the address length becomes 32-bit instead of the default 24-bit. there are two methods to exit the 4-byte mode: power-off or writing exit 4-byte mode (ex4b) instruction. all instructions are accepted normally, and just the address bit is changed form 24-bit to 32-bit. the sequence of issuing en4b instruction is: cs# goes low -> sending en4b instruction to enter 4-byte mode (automatically set 4 byte bit as ?1?) -> cs# goes high, as shown in figure 12. the instruction sequence is shown in figure 13.1 while using the enable quad peripheral interface mode (eqpi) (38h) command. figure 12. enter 4-byte mode instruction sequence diagram
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 33 en25qh256 rev. e, issue date: 2012 / 01/30 exit 4-byte mode (ex4b) (e9h) the ex4b instruction is executed to exit the 4-byte address mode and return to the default 3-bytes address mode. after sending out the ex4b instruction, the bit 2 (4 byte bit) of information register will be cleared to be ?0? to indicate the exit of the 4-byte address mode. once exiting the 4-byte address mode, the address length will return to 24-bit. the sequence of issuing ex4b instruction is: cs# goes low -> sending ex4b instruction to exit 4-byte mode (automatically clear the 4 byte bit to be ?0?) -> cs# goes high, as shown in figure 13. the instruction sequence is shown in figure 13.1 while using the enable quad peripheral interface mode (eqpi) (38h) command. figure 13. exit 4-byte mode instruction sequence diagram figure 13.1 enter / exit 4-byte mode instruction sequence under eqpi mode
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 34 en25qh256 rev. e, issue date: 2012 / 01/30 enter high bank latch mode (enhbl) (67h) the high bank latch mode (enhbl) instruction enables the first byte addresses was accessed at the memory area of higher bank (larger than 128mb) while execute the read / program / erase command, that means the address 24-bit was asserted high after entering this mode. in other words, for read / program / erase command the host system can also access the addresses from 1000000h to 1ffffff even if without inputting 4 byte address. the device default is in the memory area of lower bank (smaller than 128m); after sending out the enhbl instruction, the bit 7 (hbl bit) of information register will be automatically set to ?1? to indicate the high bank latch has been enabled. once the high bank latch mode is enable, if execute read / program / erase command, then the first byte addresses will be accessed at memory area of the higher bank (larger than 128mb) instead of the default the memory area lower bank (smaller than 128m). there are some methods that can exit the high bank latch mode: power-off, or by writing reset quad i/o (rstqio), enter 4-byte mode (en4b) and exit high bank latch mode (exhbl) instructions. the sequence of issuing enhbl instruction is: cs# goes low -> sending enhbl instruction to enter high bank latch mode (automatically set hbl bit as ?1?) -> cs# goes high, as shown in figure 14. the instruction sequence is shown in figure 15.1 while using the enable quad peripheral interface mode (eqpi) (38h) command. figure 14. enter high bank latch mode instruction sequence diagram
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 35 en25qh256 rev. e, issue date: 2012 / 01/30 exit high bank latch mode (exhbl) (98h) the exit high bank latch mode (exhbl) instruction is executed to exit the high bank latch mode and then return to the default state: the first byte addresses was accessed at memory area of lower bank (smaller than 128m) while execute the read / program / erase command. after sending out the exhbl instruction, the bit 7 (hbl bit) of information register will be cleared to be ?0? to indicate the exit of the high bank latch mode. once the exit the high bank latch mode is enable, if executed the read / program / erase command then the first byte addresses will be accessed at memory area of lower bank (smaller than 128m). the sequence of issuing exhbl instruction is: cs# goes low -> sending exhbl instruction to exit high bank latch mode (automatically clear the hbl bit to be ?0?) -> cs# goes high, as shown in figure 15. the instruction sequence is shown in figure 15.1 while using the enable quad peripheral interface mode (eqpi) (38h) command. figure 15. exit high bank latch mode instruction sequence diagram figure 15.1 enter / exit high bank latch mode instruction sequence under eqpi mode
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 36 en25qh256 rev. e, issue date: 2012 / 01/30 read data bytes (read) (03h) the device is first selected by driving chip select (cs#) low. the instruction code for the read data bytes (read) instruction is followed by a 3-byte or 4-byte address (depending on mode state), each bit being latched-in during the rising edge of serial clock (clk). then the memory contents, at that address, is shifted out on serial data output (do), each bit being shifted out, at a maximum frequency f r , during the falling edge of serial clock (clk). the instruction sequence is shown in figure 16. the first byte addresses can be at any location. to access higher address (larger than 128mb), there are two methods. one is the enter 4-byte mode (b7h) command and the other is the enter high bank latch mode (67h) command. for these methods, the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single read data bytes (read) instruction. when the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode. to enter the 4-byte mode, please refer to the enter 4-byte mode (en4b) mode section. the read data bytes (read) instruction is terminated by driving chip select (cs#) high. chip select (cs#) can be driven high at any time during data output. any read data bytes (read) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 16. read data instruction sequence diagram note: please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 37 en25qh256 rev. e, issue date: 2012 / 01/30 read data bytes at higher speed (fast_read) (0bh) the device is first selected by driving chip select (cs#) low. the instruction code for the read data bytes at higher speed (fast_read) instruction is followed by a 3-byte or 4-byte address (depending on mode state) and a dummy byte, each bit being latched-in during the rising edge of serial clock (clk). then the memory contents, at that address, is shifted out on serial data output (do), each bit being shifted out, at a maximum frequency f r , during the falling edge of serial clock (clk). the instruction sequence is shown in figure 17. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single read data bytes at higher speed (fast_read) instruction. when the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode. to enter the 4-byte mode, please refer to the enter 4-byte mode (en4b) mode section. the read data bytes at higher speed (fast_read) instruction is terminated by driving chip select (cs#) high. chip select (cs#) can be driven high at any time during data output. any read data bytes at higher speed (fast_read) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. the instruction sequence is shown in figure 17.1 while using the enable quad peripheral interface mode (eqpi) (38h) command. figure 17. fast read instruction sequence diagram note: please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 38 en25qh256 rev. e, issue date: 2012 / 01/30 figure 17.1 fast read instruction sequence under eqpi mode note: please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. dual output fast read (3bh) the dual output fast read (3bh) is similar to the standard fast read (0bh) instruction except that data is output on two pins, dq 0 and dq 1 , instead of just dq 0 . this allows data to be transferred from the en25qh256 at twice the rate of standard spi devices. the dual output fast read instruction is ideal for quickly downloading code from to ram upon power-up or for applications that cache code- segments to ram for execution. similar to the fast read instruction, the dual output fast read instruction can operation at the highest possible frequency of fr (see ac electrical characteristics). this is accomplished by adding eight ?dummy clocks after the 3-byte or 4-byte address (depending on mode state) as shown in figure 18. the dummy clocks allow the device?s internal circuits additional time for setting up the initial address. the input data during the dummy clock is ?don?t care?. however, the di pin should be high-impedance prior to the falling edge of the first data out clock. the default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode. to enter the 4-byte mode, please refer to the enter 4-byte mode (en4b) mode section.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 39 en25qh256 rev. e, issue date: 2012 / 01/30 figure 18. dual output fast read instruction sequence diagram note: please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. dual input / output fast_read (bbh) the dual i/o fast read (bbh) instruction allows for improved random access while maintaining two io pins, dq 0 and dq 1 . it is similar to the dual output fast read (3bh) instruction but with the capability to input the address bits (3-byte or 4-byte, depending on mode state) two bits per clock. this reduced instruction overhead may allow for code execution (xip) directly from the dual spi in some applications. the dual i/o fast read instruction enable double throughput of serial flash in read mode. the address is latched on rising edge of clk, and data of every two bits (interleave 2 i/o pins) shift out on the falling edge of clk at a maximum frequency. the first address can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single dual i/o fast read instruction. the address counter rolls over to 0 when the highest address has been reached. once writing dual i/o fast read instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit, as shown in figure 19. the default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode. to enter the 4-byte mode, please refer to the enter 4-byte mode (en4b) mode section.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 40 en25qh256 rev. e, issue date: 2012 / 01/30 figure 19. dual input / output fast read instruction sequence diagram note: please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 41 en25qh256 rev. e, issue date: 2012 / 01/30 quad input / output fast_read (ebh) the quad input/output fast_read (ebh) instruction is similar to the dual i/o fast read (bbh) instruction except that address (3-byte or 4-byte, depending on mode state) and data bits are input and output through four pins, dq 0 , dq 1 , dq 2 and dq 3 and six dummy clocks are required prior to the data output. the quad i/o dramatically reduces instruction overhead allowing faster random access for code execution (xip) directly from the quad spi. the quad input/output fast_read (ebh) instruction enable quad throughput of serial flash in read mode. in spi mode, the qe bit needs to be assigned through wrsr to set to ?1? before sending the spi instruction quad input/output fast_read (ebh). if the system goes into full quad i/o (eqpi), this qe bit becomes no affection since wp# and hold# function will be disabled by eqpi mode and quad input/output fast_read (ebh) will be always available in eqpi mode. the address is latching on rising edge of clk, and data of every four bits (interleave on 4 i/o pins) shift out on the falling edge of clk at a maximum frequency f r . the first address can be any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single quad input/output fast_read instruction. the address counter rolls over to 0 when the highest address has been reached. once writing quad input/output fast_read instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. the default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode. to enter the 4-byte mode, please refer to the enter 4-byte mode (en4b) mode section. the sequence of issuing quad input/output fast_read (ebh) instruction is: cs# goes low -> sending quad input/output fast_read (ebh) instruction -> 24-bit or 32-bit address (depending on mode state ) interleave on dq 3 , dq 2 , dq 1 and dq 0 -> 6 dummy cycles -> data out interleave on dq 3 , dq 2 , dq 1 and dq 0 -> to end quad input/output fast_read (ebh) operation can use cs# to high at any time during data out, as shown in figure 20. the instruction sequence is shown in figure 20.1 while using the enable quad peripheral interface mode (eqpi) (38h) command. figure 20. quad input / output fast read instruction sequence diagram note: please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 42 en25qh256 rev. e, issue date: 2012 / 01/30 figure 20.1. quad input / output fast read instruction sequence under eqpi mode note: please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. another sequence of issuing quad input/output fast_read (ebh) instruction especially useful in random access is : cs# goes low -> sending quad input/output fast_read (ebh) instruction -> 24- bit address interleave on dq 3 , dq 2 , dq 1 and dq 0 -> performance enhance toggling bit p[7:0] -> 4 dummy cycles -> data out interleave on dq 3 , dq 2 , dq 1 and dq 0 till cs# goes high -> cs# goes low (reduce quad input/output fast_read (ebh) instruction) -> 24-bit or 32-bit random access address (depending on mode state), as shown in figure 21. in the performance ? enhancing mode, p[7:4] must be toggling with p[3:0] ; likewise p[7:0] = a5h, 5ah, f0h or 0fh can make this mode continue and reduce the next quad input/output fast_read (ebh) instruction. once p[7:4] is no longer toggling with p[3:0] ; likewise p[7:0] = ffh, 00h, aah or 55h. and afterwards cs# is raised, the system then will escape from performance enhance mode and return to normal operation. while program/ erase/ write status register is in progress, quad input/output fast_read (ebh) instruction is rejected without impact on the program/ erase/ write status register current cycle. the instruction sequence is shown in figure 21.1 while using the enable quad peripheral interface mode (eqpi) (38h) command.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 43 en25qh256 rev. e, issue date: 2012 / 01/30 figure 21. quad input/output fast read enhance performance mode sequence diagram note: please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 44 en25qh256 rev. e, issue date: 2012 / 01/30 figure 21.1 quad input/output fast read enha nce performance mode sequence under eqpi mode note: please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 45 en25qh256 rev. e, issue date: 2012 / 01/30 page program (pp) (02h) the page program (pp) instruction allows bytes to be programmed in the memory. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the page program (pp) instruction is entered by driving chip select (cs#) low, followed by the in- struction code, three or four address bytes (depending on mode state) and at least one data byte on serial data input (di). if the 8 least significant address bits (a7-a0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (a7-a0) are all zero). chip select (cs#) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 22. if more than 256 bytes are sent to the device, pre- viously latched data are discarded and the last 256 data bytes are guaranteed to be programmed cor- rectly within the same page. if less than 256 data bytes are sent to device, they are correctly pro- grammed at the requested addresses without having any effects on the other bytes of the same page. the default mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode. to enter the 4-byte mode, please refer to the enter 4-byte mode (en4b) mode section. chip select (cs#) must be driven high after the eighth bit of the last data byte has been latched in, otherwise the page program (pp) instruction is not executed. as soon as chip select (cs#) is driven high, the self-timed page program cycle (whose duration is t pp ) is initiated. while the page program cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed page program cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a page program (pp) instruction applied to a page which is protected by the block protect (bp3, bp2, bp1, bp0) bits (see table 3) is not executed. the instruction sequence is shown in figure 22.1 while using the enable quad peripheral interface mode (eqpi) (38h) command. figure 22. page program instruction sequence diagram note: please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 46 en25qh256 rev. e, issue date: 2012 / 01/30 figure 22.1 program instruction sequence under eqpi mode note: please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. sector erase (se) (20h) the sector erase (se) instruction sets to 1 (ffh) all bits inside the chosen sector. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the sector erase (se) instruction is entered by driving chip select (cs#) low, followed by the in- struction code, and three or four address bytes (depending on mode state) on serial data input (di). any address inside the sector (see table 2) is a valid address for the sector erase (se) instruction. chip select (cs#) must be driven low for the entire duration of the sequence. the default mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode. to enter the 4-byte mode, please refer to the enter 4-byte mode (en4b) mode section. the instruction sequence is shown in figure 23. chip select (cs#) must be driven high after the eighth bit of the last address byte has been latched in, otherwise the sector erase (se) instruction is not executed. as soon as chip select (cs#) is driven high, the self-timed sector erase cycle (whose du- ration is t se ) is initiated. while the sector erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed sector erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a sector erase (se) instruction applied to a sector which is protected by the block protect (bp3, bp2, bp1, bp0) bits (see table 3) is not executed. the instruction sequence is shown in figure 24.1 while using the enable quad peripheral interface mode (eqpi) (38h) command.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 47 en25qh256 rev. e, issue date: 2012 / 01/30 figure 23. sector erase instruction sequence diagram note: please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. block erase (be) (d8h) the block erase (be) instruction sets to 1 (ffh) all bits inside the chosen block. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the block erase (be) instruction is entered by driving chip select (cs#) low, followed by the in- struction code, and three or four address bytes (depending on mode state) on serial data input (di). any address inside the block (see table 2) is a valid address for the block erase (be) instruction. chip select (cs#) must be driven low for the entire duration of the sequence. the default mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode. to enter the 4-byte mode, please refer to the enter 4-byte mode (en4b) mode section. the instruction sequence is shown in figure 24. chip select (cs#) must be driven high after the eighth bit of the last address byte has been latched in, otherwise the block erase (be) instruction is not executed. as soon as chip select (cs#) is driven high, the self-timed block erase cycle (whose du- ration is t be ) is initiated. while the block erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self- timed block erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a block erase (be) instruction applied to a block which is protected by the block protect (bp3, bp2, bp1, bp0) bits (see table 3) is not executed. the instruction sequence is shown in figure 24.1 while using the enable quad peripheral interface mode (eqpi) (38h) command.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 48 en25qh256 rev. e, issue date: 2012 / 01/30 figure 24. block erase instruction sequence diagram note: please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. figure 24.1 block/sector erase instruction sequence under eqpi mode note: please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 49 en25qh256 rev. e, issue date: 2012 / 01/30 chip erase (ce) (c7h/60h) the chip erase (ce) instruction sets all bits to 1 (ffh). before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the chip erase (ce) instruction is entered by driving chip select (cs#) low, followed by the instructio n code on serial data input (di). chip select (cs#) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 25. chip select (cs#) must be driven high after the eighth bit of the instruction code has been latched in, otherwise the chip erase instruction is not executed. as soon as chip select (cs#) is driven high, the self-timed chip erase cycle (whose duration is t ce ) is initiated. while the chip erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed chip erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. the chip erase (ce) instruction is executed only if all block protect (bp3, bp2, bp1, bp0) bits are 0. the chip erase (ce) instruction is ignored if one, or more blocks are protected. the instruction sequence is shown in figure 25.1 while using the enable quad peripheral interface mode (eqpi) (38h) command. figure 25. chip erase instruction sequence diagram
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 50 en25qh256 rev. e, issue date: 2012 / 01/30 figure 25.1 chip erase sequence under eqpi mode deep power-down (dp) (b9h) executing the deep power-down (dp) instruction is the only way to put the device in the lowest con- sumption mode (the deep power-down mode). it can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all write, program and erase instructions. driving chip select (cs#) high deselects the device, and puts the device in the standby mode (if there is no internal cycle currently in progress). but this mode is not the deep power-down mode. the deep power-down mode can only be entered by executing the deep power-down (dp) instruction, to reduce the standby current (from i cc1 to i cc2 , as specified in table 13.) once the device has entered the deep power-down mode, all instructions are ignored except the release from deep power-down and read device id (rdi) instruction. this releases the device from this mode. the release from deep power-down and read device id (rdi) instruction also allows the device id of the device to be output on serial data output (do). the deep power-down mode automatically stops at power-down, and the device always powers-up in the standby mode. the deep power-down (dp) instruction is entered by driving chip select (cs#) low, followed by the instruction code on serial data input (di). chip select (cs#) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 26. chip select (cs#) must be driven high after the eighth bit of the instruction code has been latched in, otherwise the deep power-down (dp) instruction is not executed. as soon as chip select (cs#) is driven high, it requires a delay of t dp before the supply current is reduced to i cc2 and the deep power-down mode is entered. any deep power-down (dp) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 51 en25qh256 rev. e, issue date: 2012 / 01/30 figure 26. deep power-down instruction sequence diagram release from deep power-down and read device id (rdi) once the device has entered the deep power-down mode, all instructions are ignored except the release from deep power-down and read device id (rdi) instruction. executing this instruction takes the device out of the deep power-down mode. please note that this is not the same as, or even a subset of, the jedec 16-bit electronic signature that is read by the read identifier (rdid) instruction. the old-style electronic signature is supported for reasons of backward compatibility, only, and should not be used for new designs. new designs should, instead, make use of the jedec 16-bit electronic signature, and the read identifier (rdid) instruction. when used only to release the device from the power-down state, the instruction is issued by driving the cs# pin low, shifting the instruction code ?abh? and driving cs# high as shown in figure 27. after the time duration of t res1 (see ac characteristics) the device will resume normal operation and other instructions will be accepted. the cs# pin must remain high during the t res1 time duration. when used only to obtain the device id while not in the power-down state, the instruction is initiated by driving the cs# pin low and shifting the instruction code ?abh? followed by 3-dummy bytes. the device id bits are then shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 28. the device id value for the en25qh256 are listed in table 5. the device id can be read continuously. the instruction is completed by driving cs# high. when chip select (cs#) is driven high, the device is put in the stand-by power mode. if the device was not previously in the deep power-down mode, the transition to the stand-by power mode is immediate. if the device was previously in the deep power-down mode, though, the transition to the standby power mode is delayed by t res2 , and chip select (cs#) must remain high for at least t res2 (max), as specified in table 15. once in the stand-by power mode, the device waits to be selected, so that it can receive, decode and execute instructions. except while an erase, program or write status register cycle is in progress, the release from deep power-down and read device id (rdi) instruction always provides access to the 8bit device id of the device, and can be applied even if the deep power-down mode has not been entered. any release from deep power-down and read device id (rdi) instruction while an erase, program or write status register cycle is in progress, is not decoded, and has no effect on the cycle that is in progress.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 52 en25qh256 rev. e, issue date: 2012 / 01/30 figure 27. release power-down instruction sequence diagram figure 28. release power-down / device id instruction sequence diagram read manufacturer / device id (90h) the read manufacturer/device id instruction is an alternative to the release from power-down / device id instruction that provides both the jedec assigned manufacturer id and the specific device id. the read manufacturer/device id instruction is very similar to the release from power-down / device id instruction. the instruction is initiated by driving the cs# pin low and shifting the instruction code ?90h? followed by a 24-bit or 32-bit address (depending on mode state) of 000000h. after which, the manufacturer id for eon (1ch) and the device id are shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 29. the device id values for the en25qh256 are listed in table 5. if the 24-bit or 32-bit address (depending on mode state) is initially set to 000001h the device id will be read first the instruction sequence is shown in figure 29.1 while using the enable quad peripheral interface mode (eqpi) (38h) command.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 53 en25qh256 rev. e, issue date: 2012 / 01/30 figure 29. read manufacturer / device id diagram note: please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. figure 29.1. read manufacturer / device id diagram under eqpi mode note: please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 54 en25qh256 rev. e, issue date: 2012 / 01/30 read identification (rdid) (9fh) the read identification (rdid) instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. the device identification indicates the memory type in the first byte , and the memory capacity of the device in the second byte . any read identification (rdid) instruction while an erase or program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. the read identification (rdid) instruction should not be issued while the device is in deep power down mode. the device is first selected by driving chip select low. then, the 8-bit instruction code for the instruction is shifted in. this is followed by the 24-bit device identification, stored in the memory, being shifted out on serial data output, each bit being shifted out during the falling edge of serial clock. the instruction sequence is shown in figure 30. the read identification (rdid) instruction is terminated by driving chip select high at any time during data output. when chip select is driven high, the device is put in the standby power mode. once in the standby power mode, the device waits to be selected, so that it can receive, decode and execute instructions. the instruction sequence is shown in figure 30.1 while using the enable quad peripheral interface mode (eqpi) (38h) command. figure 30. read identification (rdid)
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 55 en25qh256 rev. e, issue date: 2012 / 01/30 figure 30.1. read identification (rdid) under eqpi mode enter otp mode (3ah) this flash has an extra 512 bytes otp sector, user must issue enter otp mode command to read, program or erase otp sector. after entering otp mode, srp bit becomes otp_lock bit and can be read with rdsr command. program / erase command will be disabled when otp_lock bit is ?1? wrsr command will ignore the input data and program otp_lock bit to 1. user must clear the protect bits before enter otp mode. otp sector can only be program and erase before otp_lock bit is set to ?1? and bp [3:0] = ?0000? . while in otp mode, array access is not allowed. user can use wrdi (04h) command to exit otp mode. while in otp mode, user can use sector erase (20h) command only to erase otp data. the instruction sequence is shown in figure 31.1 while using the enable quad peripheral interface mode (eqpi) (38h) command. table 8. otp sector address sector size address range 512 byte xxx000h ? xxx1ffh
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 56 en25qh256 rev. e, issue date: 2012 / 01/30 figure 31. enter otp mode sequence figure 31.1 enter otp mode sequence under eqpi mode
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 57 en25qh256 rev. e, issue date: 2012 / 01/30 read sfdp mode and unique id number (5ah) read sfdp mode en25qh256 features serial flash discoverable parameters (sfdp) mode. host system can retrieve the operating characteristics, structure and vendor specified information such as identifying information, memory size, operating voltage and timing information of this device by sfdp mode. the device is first selected by driving chip select (cs#) low. the instruction code for the read sfdp mode is followed by a 3-byte address (a23-a0) and a dummy byte, each bit being latched-in during the rising edge of serial clock (clk). then the memory contents, at that address, is shifted out on serial data output (do), each bit being shifted out, at a maximum frequency fr, during the falling edge of serial clock (clk). the instruction sequence is shown in figure 32. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single serial flash discoverable parameters (sfdp) instruction. when the highest address is reached, the address counter rolls over to 0x00h, allowing the read sequence to be continued indefinitely. the serial flash discoverable parameters (sfdp) instruction is terminated by driving chip select (cs#) high. chip select (cs#) can be driven high at any time during data output. any read data bytes at serial flash discoverable parameters (sfdp) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 32. read sfdp mode instruction sequence diagram note: please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 58 en25qh256 rev. e, issue date: 2012 / 01/30 table 9. serial flash discoverable parameters (sfdp) signature and parameter identification data value (advanced information) description address (h) (byte mode) address (bit) data comment 00h 07 : 00 53h 01h 15 : 08 46h 02h 23 : 16 44h sfdp signature 03h 31 : 24 50h signature [31:0]: hex: 50444653 sfdp minor revision number 04h 07 : 00 00h star from 0x00 sfdp major revision number 05h 15 : 08 01h star from 0x01 number of parameter headers (nph) 06h 23 : 16 00h 1 parameter header unused 07h 31 : 24 ffh reserved id number 08h 07 : 00 00h jedec id parameter table minor revision number 09h 15 : 08 00h star from 0x00 parameter table major revision number 0ah 23 : 16 01h star from 0x01 parameter table length (in dw) 0bh 31 : 24 09h 9 dwords 0ch 07 : 00 30h 0dh 15 : 08 00h parameter table pointer (ptp) 0eh 23 : 16 00h 000030h unused 0fh 31 : 24 ffh reserved
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 59 en25qh256 rev. e, issue date: 2012 / 01/30 table 10. parameter id (0) (advanced information) 1/9 description address (h) (byte mode) address (bit) data comment 00 block / sector erase sizes identifies the erase granularity for all flash components 01 01b 00 = reserved 01 = 4kb erase 10 = reserved 11 = 64kb erase write granularity 02 1b 0 = no, 1 = yes write enable instruction required for writing to volatile status register 03 write enable opcode select for writing to volatile status register 04 00b 00 = n/a 01 = use 50h opcode 11 = use 06h opcode 05 06 unused 30h 07 111b reserved 08 09 10 11 12 13 14 4 kilo-byte erase opcode 31h 15 20h 4 kb erase support (ffh = not supported) supports (1-1-2) fast read device supports single input opcode & address and quad output data fast read 16 1b 0 = not supported 1 = supported 17 address byte n umber of bytes used in addressing for flash arr a w rite and erase. 18 01b 00 = 3-byte 01 = 3- or 4-byte (e.g. defaults to 3-byte mode; enters 4-byte mode on command) 10 = 4-byte 11 = reserved supports double transfer rate (dtr) clocking indicates the device supports some type of double transfer rate clocking. 19 0b 0 = not supported 1 = supported supports (1-2-2) fast read device supports single input opcode, dual input address, and quad output data fast read 20 1b 0 = not supported 1 = supported supports (1-4-4) fast read device supports single input opcode, quad input address, and quad output data fast read 21 1b 0 = not supported 1 = supported supports (1-1-4) fast read device supports single input opcode & address and quad output data fast read 22 0b 0 = not supported 1 = supported unused 32h 23 1b reserved 24 25 26 27 28 29 30 unused 33h 31 ffh reserved
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 60 en25qh256 rev. e, issue date: 2012 / 01/30 table 10. parameter id (0) (advanced information) 2/9 description address (h) (byte mode) address (bit) data comment flash memory density 37h : 34h 31 : 00 0fffffffh 256 mbits table 10. parameter id (0) (advanced information) 3/9 description address (h) (byte mode) address (bit) data comment 00 01 02 03 (1-4-4) fast read number of wait states (dummy clocks) needed before valid output 04 00100b 4 dummy clocks 05 06 quad input address quad output (1-4- 4) fast read number of mode bits 38h 07 010b 8 mode bits 08 09 10 11 12 13 14 (1-4-4) fast read opcode opcode for single input opcode, quad input address, and quad output data fast read. 39h 15 ebh 16 17 18 19 (1-1-4) fast read number of wait states (dummy clocks) needed before valid output 20 00000b not supported 21 22 (1-1-4) fast read number of mode bits 3ah 23 000b not supported (1-1-4) fast read opcode opcode for single input opcode & address and quad output data fast read. 3bh 31 : 24 ffh not supported
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 61 en25qh256 rev. e, issue date: 2012 / 01/30 table 10. parameter id (0) (advanced information) 4/9 description address (h) (byte mode) address (bit) data comment 00 01 02 03 (1-1-2) fast read number of wait states (dummy clocks) needed before valid output 04 01000b 8 dummy clocks 05 06 (1-1-2) fast read number of mode bits 3ch 07 000b not supported (1-1-2) fast read opcode opcode for single input opcode & address and dual output data fast read. 3dh 15 : 08 3bh 16 17 18 19 (1-2-2) fast read number of wait states (dummy clocks) needed before valid output 20 00100b 4 dummy clocks 21 22 (1-2-2) fast read number of mode bits 3eh 23 000b not supported (1-2-2) fast read opcode opcode for single input opcode, dual input address, and dual output data fast read. 3fh 31 : 24 bbh table 10. parameter id (0) (advanced information) 5/9 description address (h) (byte mode) address (bit) data comment supports (4-4-4) fast read device supports quad input opcode & address and quad output data fast read. 00 0b 0 = not supported 1 = supported 01 02 reserved. these bits default to all 1?s 03 111b reserved supports (2-2-2) fast read device supports dual input opcode & address and dual output data fast read. 04 1b 0 = not supported 1 = supported (eqpi mode) 05 06 reserved. these bits default to all 1?s 40h 07 111b reserved reserved. these bits default to all 1?s 43h : 41h 31 : 08 ffh reserved
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 62 en25qh256 rev. e, issue date: 2012 / 01/30 table 10. parameter id (0) (advanced information) 6/9 description address (h) (byte mode) address (bit) data comment reserved. these bits default to all 1?s 45h : 44h 15 : 00 ffh reserved 16 17 18 19 (2-2-2) fast read number of wait states (dummy clocks) needed before valid output 20 00000b not supported 21 22 (2-2-2) fast read number of mode bits 46h 23 000b not supported (2-2-2) fast read opcode opcode for dual input opcode & address and dual output data fast read. 47h 31 : 24 ffh not supported table 10. parameter id (0) (advanced information) 7/9 description address (h) (byte mode) address (bit) data comment reserved. these bits default to all 1?s 49h : 48h 15 : 00 ffh reserved 16 17 18 19 (4-4-4) fast read number of wait states (dummy clocks) needed before valid output 20 00100b 4 dummy clocks 21 22 (4-4-4) fast read number of mode bits 4ah 23 010b 8 mode bits (4-4-4) fast read opcode opcode for quad input opcode/address, quad output data fast read. 4bh 31 : 24 ebh must enter eqpi mode firstly table 10. parameter id (0) (advanced information) 8/9 description address (h) (byte mode) address (bit) data comment sector type 1 size 4ch 07 : 00 0ch 4 kb sector type 1 opcode 4dh 15 : 08 20h sector type 2 size 4eh 23 : 16 00h not supported sector type 2 opcode 4fh 31 : 24 ffh not supported table 10. parameter id (0) (advanced information) 9/9 description address (h) (byte mode) address (bit) data comment sector type 3 size 50h 07 : 00 10h 64 kb sector type 3 opcode 51h 15 : 08 d8h sector type 4 size 52h 23 : 16 00h not supported sector type 4 opcode 53h 31 : 24 ffh not supported
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 63 en25qh256 rev. e, issue date: 2012 / 01/30 read unique id number the read unique id number instruction accesses a factory-set read-only 96-bit number that is unique to each en25qh256 device. the id number can be used in conjunction with user software methods to help prevent copying or cloning of a system. the read unique id instruction is initiated by driving the cs# pin low and shifting the instruction code ?5ah? followed by a three bytes of addresses, 0x80h, and one byte of dummy clocks. after which, the 96-bit id is shifted out on the falling edge of clk as shown in figure 32. table 11. unique id number description address (h) (byte mode) address (bit) data comment unique id number 80h : 8bh 95 : 00 by die power-up timing figure 33. power-up timing table 12. power-up timing and write inhibit threshold symbol parameter min. max. unit t vsl (1) vcc(min) to cs# low 10 s t puw (1) time delay to write instruction 1 10 ms vwi (1) write inhibit voltage 1 2.5 v note: 1.the parameters are characterized only. 2. vcc (max.) is 3.6v and vcc (min.) is 2.7v initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). the status register contains 00h (all status register bits are 0).
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 64 en25qh256 rev. e, issue date: 2012 / 01/30 table 13. dc characteristics (t a = - 40c to 85c; v cc = 2.7-3.6v) symbol parameter test conditions min. max. unit i li input leakage current - 2 a i lo output leakage current - 2 a i cc1 standby current cs# = v cc , v in = v ss or v cc - 20 a i cc2 deep power-down current cs# = v cc , v in = v ss or v cc - 20 a i cc3 operating current (read) clk = 0.1 v cc / 0.9 v cc at 80mhz, dq = open - 20 ma i cc4 operating current (pp) cs# = v cc - 28 ma i cc5 operating current (wrsr) cs# = v cc - 18 ma i cc6 operating current (se) cs# = v cc - 25 ma i cc7 operating current (be) cs# = v cc - 25 ma v il input low voltage ? 0.5 0.2 v cc v v ih input high voltage 0.7v cc v cc +0.4 v v ol output low voltage i ol = 1.6 ma - 0.4 v v oh output high voltage i oh = ?100 a v cc -0.2 - v table 14. ac measurement conditions symbol parameter min. max. unit c l load capacitance 20 pf input rise and fall times 5 ns input pulse voltages 0.2 v cc to 0.8 v cc v input timing refe rence voltages 0.3 v cc to 0.7 v cc v output timing reference voltages v cc / 2 v figure 34. ac measurement i/o waveform
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 65 en25qh256 rev. e, issue date: 2012 / 01/30 table 15. ac characteristics (t a = - 40c to 85c; v cc = 2.7-3.6v) symbol alt parameter min typ max unit serial clock frequency for: fast_read, pp, se, be, dp, res, wren, wrdi, wrsr d.c. - 80 mhz f r f c serial clock frequency for: dual output fast read d.c. - 80 mhz f r serial clock frequency for read, quad i/o fast read, rdsr, rdid, d.c. - 50 mhz t ch 1 serial clock high time 5 - - ns t cl 1 serial clock low time 5 - - ns t clch 2 serial clock rise time (slew rate) 0.1 - - v / ns t chcl 2 serial clock fall time (slew rate) 0.1 - - v / ns t slch t css cs# active setup time (relative to clk) 5 - - ns t chsh cs# active hold time (relative to clk) 5 - - ns t shch cs# not active setup time (relative to clk) 5 - - ns t chsl cs# not active hold time (relative to clk) 5 - - ns t shsl t csh cs# high time for read cs# high time for program/erase 15 50 - - ns ns t shqz 2 t dis output disable time - - 6 ns t clqx t ho output hold time 0 - - ns t dvch t dsu data in setup time 2 - - ns t chdx t dh data in hold time 5 - - ns t hlch hold# low setup time ( relative to clk ) 5 ns t hhch hold# high setup time ( relative to clk ) 5 ns t chhh hold# low hold time ( relative to clk ) 5 ns t chhl hold# high hold time ( relative to clk ) 5 ns t hlqz 2 t hz hold# low to high-z output 6 ns t hhqx 2 t lz hold# high to low-z output 6 ns t clqv t v output valid from clk - - 10 ns t whsl 3 write protect setup time before cs# low 20 - - ns t shwl 3 write protect hold time after cs# high 100 - - ns t dp 2 cs# high to deep power-down mode - - 3 s t res1 2 cs# high to standby mode without electronic signature read - - 3 s t res2 2 cs# high to standby mode with electronic signature read - - 1.8 s t w write status register cycle time - 10 50 ms t pp page programming time - 0.8 5 ms t se sector erase time - 50 300 ms t be block erase time - 0.4 2 s t ce chip erase time - 100 280 s wip = write operation - - 28 s t sr software reset latency wip = not in write operation - - 0 s note: 1. t ch + t cl must be greater than or equal to 1/ f c 2. value guaranteed by characterization, not 100% tested in production. 3. only applicable as a constraint for a write status register instruction when status register protect bit is set at 1.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 66 en25qh256 rev. e, issue date: 2012 / 01/30 figure 35. serial output timing figure 36. input timing figure 37. hold timing
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 67 en25qh256 rev. e, issue date: 2012 / 01/30 absolute maximum ratings stresses above the values so mentioned above may cause permanent damage to the device. these values are for a stress rating only and do not imply that the device should be operated at conditions up to or above these values. exposure of the device to the maximum rating values for extended periods of time may adversely affect the device reliability. parameter value unit storage temperature -65 to +150 c plastic packages -65 to +125 c output short circuit current 1 200 ma input and output voltage (with respect to ground) 2 -0.5 to +4.0 v vcc -0.5 to +4.0 v notes: 1. no more than one output shorted at a time. duration of the short circuit should not be greater than one second. 2. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, inputs may undershoot v ss to ?1.0v for periods of up to 50ns and to ?2.0 v for periods of up to 20ns. see figure below. maximum dc voltage on output and i/o pins is v cc + 0.5 v. during voltage transitions, outputs may overshoot to v cc + 1.5 v for periods up to 20ns. see figure below. recommended operating ranges 1 parameter value unit ambient operating temperature industrial devices -40 to 85 c operating supply voltage vcc full: 2.7 to 3.6 v notes: 1. recommended operating ranges define those limits between which the functionality of the device is guaranteed. vcc +1.5v maximum negative overshoot waveform maximum positive overshoot waveform
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 68 en25qh256 rev. e, issue date: 2012 / 01/30 table 16. data retention and endurance parameter description test conditions min unit 150c 10 years data retention time 125c 20 years erase/program endurance -40 to 85 c 100k cycles table 17. capacitance ( v cc = 2.7-3.6v) parameter symbol parameter description test setup max unit c in input capacitance v in = 0 6 pf c out output capacitance v out = 0 8 pf note : sampled only, not 100% tested, at t a = 25c and a frequency of 20mhz.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 69 en25qh256 rev. e, issue date: 2012 / 01/30 package mechanical figure 38. vdfn 8 ( 6x8 mm ) min. nor max a 0.70 0.75 0.80 a1 0.00 0.02 0.05 a2 - - - 0.20 - - - d 7.908.008.10 e 5.906.006.10 d1 4.65 4.70 4.75 e1 4.55 4.60 4.65 e - - - 1.27 - - - b 0.350.400.48 l 0.4 0.50 0.60 note : 1. coplanarit y : 0.1 mm symbol dimension in mm notice: this package can?t contact to metal trace or pad on board due to expose metal pad underneath the package.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 70 en25qh256 rev. e, issue date: 2012 / 01/30 figure 39. 16 lead sop 300 mil min. nor max a - - - - - - 2.65 a1 0.10 0.20 0.30 a2 2.25 - - - 2.40 c 0.20 0.25 0.30 d 10.10 10.30 10.50 e 10.00 - - - 10.65 e1 7.40 7.50 7.60 e - - - 1.27 - - - b 0.31 - - - 0.51 l0.4- - -1.27 0 0 5 0 8 0 note : 1. co p lanarit y : 0.1 mm symbol dimension in mm
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 71 en25qh256 rev. e, issue date: 2012 / 01/30 figure 40. 24-ball ball grid array (6 x 8 mm) package mi n. nor max a - - - - - - 1.20 a1 0. 2 7 - - - 0. 3 7 a2 a3 d e d1 - - - 3.00 - - - e1 - - - 5.00 - - - e - - - 1.00 - - - b - - - 0.40 - - - di me nsi on i n mm symbol 0.21 ref 0.54 ref 6 bsc 8 bsc
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 72 en25qh256 rev. e, issue date: 2012 / 01/30 purpose eon silicon solution inc. (hereinafter called ?eon?) is going to provide its products? top marking on ics with < cfeon > from january 1 st , 2009, and without any change of the part number and the compositions of the ics. eon is still keeping the promise of quality for all the products with the same as that of eon delivered before. please be advised with the change and appreciate your kindly cooperation and fully support eon?s product family. eon products? top marking cfeon top marking example: for more information please contact your local sales office for additional information about eon memory solutions. cfeon part number: xxxx-xxx lot number: xxxxx date code: xxxxx
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 73 en25qh256 rev. e, issue date: 2012 / 01/30 ordering information en25qh256 - 80 f i p packaging content p = rohs compliant temperature range i = industrial (-40 c to +85 c) package y = 8-pin vdfn (6x8mm) f = 16-pin 300mil sop bb = 24-ball ball grid array (6 x 8 mm) speed 80 = 80 mhz base part number en = eon silicon solution inc. 25qh = 3v serial flash with 4kb uniform-sector, dual and quad i/o 256 = 256 megabit (32768k x 8)
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 74 en25qh256 rev. e, issue date: 2012 / 01/30 revisions list revision no description date a initial release 2011/01/10 b 1. add the note ?5. this flow cannot release the device from deep power down mode.? on page 24. 2. correct the typo of 6 dummy clocks for ebh command on page 41. 3. update read sfdp mode and add unique id number (5ah) description on page 57. 2011/06/07 c 1. update standard spi speed from 104mhz to 80mhz. 2. update table 16. dc characteristics on page 63. 3. update table 18. ac characteristics on page 64. 4. update ordering information on page 72. 2011/09/01 d 1. update figure 2. block diagram on page 4. 2. update the serial flash discoverable parameters (sfdp) table on page 58, 59, 60, 61 and 62. 2011/11/28 e update unique id number from 64 bits to 96 bits on page 63. 2012/01/30

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